1. Field of the Invention
This invention relates to a lateral transistor structure and to processes for fabricating it, and in particular to a lateral transistor structure having a self-aligned base/base contact and a very narrow base width compared to existing lateral transistors.
2. Prior Art
Most present high performance transistor structures rely upon vertical transistors in which the active junctions are formed parallel to the surface of the silicon, and the emitter to collector currents therefore flow vertically. Such structures provide precise yet straight-forward control of the transistor base width by virtue of the diffusion processes utilized in fabricating them. Existing diffusion processes permit manufacture of vertical bipolar transistors having a base width of 5,000 angstroms. Such transistors have a gain of approximately 100 and operate at frequencies up to approximately one gigaHertz.
The maximum switching frequency for such transistors has been limited by primarily two parameters--the total base resistance and the collector-base capacitance. Nonetheless using three micron integrated circuit layout rules these parameters have been low enough to permit switching speeds on the order of 1 to 3 nanoseconds. As integrated circuit processing technology moves closer to permitting 1 micron layout rules, very shallow junctions, and very narrow base widths, it is expected that transistors may usefully operate at frequencies of up to 10 gigaHertz. At such high frequencies switching performance will be almost completely dependent upon base resistance and collector-base capacitance.
Lateral transistors, of course, are well known. Different techniques of integrated circuit manufacture have been used to fabricate such transistors. One well known technique is to use a double diffusion process, for example, as taught by Schinella and Anthony in U.S. Pat. Nos. 3,919,005 or 3,945,857. Using this process, the transistor base is created by laterally and vertically diffusing into an epitaxial semiconductor layer formed over a buried layer, a base impurity of the desired conductivity type. Much of the base is then counter doped with a second diffusion of opposite conductivity type for the emitter or collector of the transistor. Suitably controlled, the second diffusion overdopes all but a narrow portion of the base impurity, resulting in the base width of the transistor being that portion of the structure not overdoped by the second diffusion. The semiconductor substrate forms the other of the collector or emitter. Contact to the base is made by the buried layer, while contact to the buried layer is made elsewhere by a doped region extending through the epitaxial layer to the buried layer. The doped region is the same conductivity type as the buried layer.
A second technique for fabricating lateral transistors in integrated circuit structures has been to deposit a line of masking material on the surface of an epitaxial layer and then diffuse impurities for the collector and emitter toward each other in the substrate from opposite sides of the line. The base region will be the portion of the epitaxial layer between the diffusion fronts of the emitter and the collector. Electrical contact to the base is made through a buried layer. Unfortunately, all of the above techniques suffer from several disadvantages. Each technique, because of the buried layer and the need to make electrical contact to it, creates a transistor structure which occupies an undesirably large area on the wafer. None of the techniques allows sufficient control over the processes involved to achieve base widths less than 1 micron. Further, diffusing the collector-emitter impurities for even slightly too long will overdope the semiconductor material which would other-wise form the base, and destroy the function of the transistor.